Altera cyclone V Technical Reference page 1594

cv_5v4
2016.10.28
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30 29
15 14 13
PPS_Control Fields
Bit Name
6:5
trgtmodsel0
4
ppsen0
3:0
ppsctrl_ppscmd
Ethernet Media Access Controller
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
28 27 26 25
12 11 10 9
Reserved
This field indicates the Target Time registers (register
455 and 456) mode for PPS0 output signal
Value
0x0 Target Time regs generate interrupt event.
0x2 Target Time gen. interr event and sig pps0
0x3 Target Time No inter just start and stop sig
pps0
When set low, Bits[3:0] function as PPSCTRL
(backward compatible). When set high, Bits[3:0]
function as PPSCMD.
Value
0x0
0x1
PPSCTRL0: PPS0 Output Frequency
Control
This field controls the frequency of
the PPS0 output (ptp_pps_o[0])
signal. The default value of PPSCTRL
is 0000, and the PPS output is 1
pulse (of width clk_ptp_i) every
second. For other values of PPSCTRL,
the PPS output becomes a generated
Bit Fields
24 23 22 21
Reserved
8 7 6
trgtmodsel0
RW 0x0
Description
Description
Description
Bits[3:0] function as ppsctrl0
Bits[3:0] function as ppscmd
PPS_Control
20 19 18
5 4 3 2
ppsen ppsctrl_ppscmd
0
RW 0x0
RW
0x0
Access
17-379
17 16
1 0
Reset
RW 0x0
RW 0x0
RW 0x0
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