Altera cyclone V Technical Reference page 1508

Hard processor system
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cv_5v4
2016.10.28
Access:
RO
31
30
15
14
rxfifooverflow Fields
Bit
31:0
cnt
rxvlanframes_gb
Number of good and bad VLAN frames received
Module Instance
emac0
emac1
Offset:
0x1D8
Access:
RO
31
30
15
14
rxvlanframes_gb Fields
Bit
31:0
cnt
Ethernet Media Access Controller
Send Feedback
29
28
27
26
13
12
11
10
Name
Number of missed received frames due to FIFO
overflow
0xFF700000
0xFF702000
29
28
27
26
13
12
11
10
Name
Number of good and bad VLAN frames received
Bit Fields
25
24
23
22
cnt
RO 0x0
9
8
7
6
cnt
RO 0x0
Description
Base Address
Bit Fields
25
24
23
22
cnt
RO 0x0
9
8
7
6
cnt
RO 0x0
Description
rxvlanframes_gb
21
20
19
18
5
4
3
2
Access
Register Address
0xFF7001D8
0xFF7021D8
21
20
19
18
5
4
3
2
Access
17-293
17
16
1
0
Reset
RO
0x0
17
16
1
0
Reset
RO
0x0
Altera Corporation

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