Altera cyclone V Technical Reference page 1473

Hard processor system
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17-258
MMC_Transmit_Interrupt_Mask
Bit
15
txmcolgfim
14
txscolgfim
13
txuflowerfim
12
txbcgbfim
11
txmcgbfim
Altera Corporation
Name
Setting this bit masks the interrupt when the
txmulticol_g counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the
txsinglecol_g counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the txunder‐
flowerror counter reaches half of the maximum value
or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the txbroad‐
castframes_gb counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Setting this bit masks the interrupt when the txmulti‐
castframes_gb counter reaches half of the maximum
value or the maximum value.
Value
0x0
0x1
Description
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
Description
counter < half max
counter >= half max or max
2016.10.28
Access
Reset
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
Ethernet Media Access Controller
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cv_5v4

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