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2–4
Table 2–2. A/D Converter Clock Select Jumper (J3, J7) Settings (Part 2 of 2)
Clock Source
Board Reference
No Clock
Notes to
Table
2–2:
(1) Refer to the appendices for FPGA pin numbers for specific development boards.
(2) On the schematic, MUX (U9) output signal names are ADA_CLK_SEL_P and ADA_CLK_SEL_N.
(3) On the schematic, MUX (U10) output signal names are ADB_CLK_SEL_P and ADB_CLK_SEL_N.
Power Down Select Jumper (J2, J6)
The power down configuration of the A/D converter is selectable through J2 (channel
A) or J6 (channel B).
converters should be powered down when not used to reduce spurious noise output.
Table 2–3. Power Down Select Jumper Settings for AD9254 A/D Converter (U1, U2)
A/D Converter
U1 (Channel A)
U1 (Channel A)
U2 (Channel B)
U2 (Channel B)
Note to
Table
2–3:
(1) If jumper pins are left open, A/D converter will be in normal state.
D/A Converter Clock Select Jumper (J15, J17)
Table 2–4
the D/A converter clock.
Table 2–4. D/A Converter Clock Select Jumper (J15, J17) Settings
Clock Source
Board Reference
FPGA Clock
HSMC Connector
FPGA Clock
HSMC Connector
External Clock
External Clock Input SMA
No Clock
Notes to
Table
2–4:
(1) On the schematic, MUX (U11) output signal names are DAC_CLK_1_P and DAC_CLK_1_N.
(2) On the schematic, MUX (U12) output signal names are DAC_CLK_2_P and DAC_CLK_2_N.
Data Conversion HSMC Reference Manual
Schematic Signal Name
(1),
—
NO_CLK_P
NO_CLK_N
Table 2–3
lists the jumper settings for power down options. A/D
Jumper Settings
(1)
J2 Jumper OFF
J2 Jumper ON
J6 Jumper OFF
J6 Jumper ON
lists the J15 (channel A) and J17 (channel B) jumper settings used to select
Schematic Signal Name
FPGA_CLK_A_P
FPGA_CLK_A_N
FPGA_CLK_B_P
FPGA_CLK_B_N
XT_IN_P
XT_IN_N
—
NO_CLK_P
NO_CLK_N
Chapter 2: Board Components and Interfaces
Configuration, Status, and Setup Elements
A/D Converter Clock Select (J3 or J7)
(2), (3)
Pins 1 and 3
Pins 2 and 4
Description
A/D converter channel A in normal (operational) state
A/D converter channel A in power down
A/D converter channel B in normal (operational) state
A/D converter channel B in power down
D/A Converter Clock Select (J15
(1)
,
(2)
Pins 3 and 5
Pins 4 and 6
Pins 1 and 3
Pins 4 and 6
Pins 3 and 5
Pins 2 and 4
Pins 1 and 3
Pins 2 and 4
© November 2008 Altera Corporation
Jumper Setting
or J17) Jumper Setting
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