L2 Cache - Altera Cyclone V Device Handbook

6-28
Memory Region Remap
Memory Region Remap
The ACP ID mapper has 1 GB of address space, which is by default a view into the bottom 1 GB of SDRAM.
The mapper also allows transactions to be routed to different 1 GB-sized memory regions, called pages, in
both dynamic and fixed modes. The two most significant bits of incoming 32-bit AXI address signals are
replaced with the 2-bit user-configured address page decode information. The page decoder uses the values
shown in Table
Table 6-6: Page Decoder Values
0
1
2
3
With this page decode information, a master can read or write to any 1 GB region of the 4 GB memory space
while maintaining cache coherency with the MPU subsystem.
Using this feature, a debugger can have a coherent view into main memory, without having to stop the
processor. For example, at reset the DAP input ID (0x001) is mapped to output ID 2, so the debugger can
vary the 1 GB window that the DAP accesses without affecting any other traffic flow to the ACP.

L2 Cache

The MPU subsystem includes a secondary 512 KB L2 shared, unified cache memory.
Functional Description
The L2 cache is much larger than the L1 cache. The L2 cache has significantly lower latency than external
memory. The L2 cache is up to eight-way associative, configurable down to one-way (direct mapped). Like
the L1 cache, the L2 cache can be locked by cache line, locked by way, or locked by bus master.
The L2 cache implements error correction codes (ECCs) and ECC error reporting. The cache can report a
number of events to the processor and operating system.
Cache Controller Configuration
The L2 cache consists of the ARM L2C-310 L2 cache controller configured as follows:
• 512 KB total memory
• Eight-way associativity
• Physically addressed, physically tagged
• Line length of 32 bytes
• Critical first word linefills
• Support for all AXI cache modes, as shown in
Altera Corporation
6-6.
Page Address Range
0x00000000—0x3FFFFFFF
0x40000000—0x7FFFFFFF
0x80000000—0xBFFFFFFF
0xC0000000—0xFFFFFFFF
Table 6-7.
Cortex-A9 Microprocessor Unit Subsystem
cv_54006
2013.12.30
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