Resets; Initialization; Protocol Details - Altera Cyclone V Device Handbook

cv_54008
2013.12.30

Resets

The SDRAM controller subsystem supports a full reset (cold reset) and a warm reset, which may or may not
preserve the contents of memory.
To preserve memory contents, the reset manager can request that the single-port controller place the SDRAM
in self-refresh mode prior to issuing the warm reset. If memory contents are preserved, the PHY and the
memory timing logic is not reset, but the rest of the controller is reset.
Related Information
Reset Manager

Initialization

The SDRAM controller subsystem has control and status registers (CSRs) which control the operation of
the controller including DRAM type, DRAM timing parameters and relative port priorities. It also has a
small set of bits which depend on the FPGA fabric to configure ports between the memory controller and
the FPGA fabric; these bits are set for you when you configure your implementation using the HPS GUI in
Qsys.
The CSRs are configured using a dedicated slave interface, which provides accesses to registers. This region
controls all SDRAM operation, MPFE scheduler configuration, and PHY calibration.
The FPGA fabric interface configuration is programmed into the FPGA fabric and the values of these register
bits can be read by software. The ports can be configured without software developers needing to know how
the FPGA-to-HPS SDRAM interface has been configured.

Protocol Details

The following topics summarize signals for the Avalon-MM Bidirectional port, Avalon-MM Write Port,
Avalon-MM Read Port, and AXI port.
Avalon-MM Bidirectional Port
The Avalon-MM bidirectional ports are standard Avalon-MM ports used to dispatch read and write
operations. Each configured Avalon-MM bidirectional port consists of the signals listed in the following
table.
SDRAM Controller Subsystem
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Resets
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