Coresight Debug And Trace Address Map And Register Definitions - Altera Cyclone V Device Handbook

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CoreSight Debug and Trace Address Map and Register Definitions

Port Name Clock Source
Reset manager
nCTMRESET
Reset manager
nPOTRST
JTAG interface
nTRST
Reset manager
TRESETn
The ETR stall enable field (etrstallen) of the ctrl register in the reset manager controls whether the
ETR is requested to stall its AXI master interface to the L3 interconnect before a warm or debug reset.
The level 4 (L4) watchdog timers can be paused during debugging to prevent reset while the processor is
stopped at a breakpoint.
Related Information
• Reset Manager
• Watchdog Timer
• Info center
For more information about the CoreSight port names, refer to the CoreSight Technology System Design
Guide.
CoreSight Debug and Trace Address Map and Register Definitions
The address map resides in the hps.html file that accompanies this handbook volume. The register definitions
reside in separate ARM documentation. Click the hps.htmllink below to open the file.
To view the debug-related module descriptions and base addresses, click the hps.html link below to search
for the following modules :
• stm
• dap
• dmanonsecure
• dmasecure
• mpuscu
• mpul2
To then view the register and field descriptions, click the link in the module description to access the
appropriate ARM documentation. The register addresses are offsets relative to the base address of each
module instance.
Related Information
• Introduction to Cyclone V Hard Processor System (HPS)
The base addresses of all modules are also listed in the Introduction to the Hard Processor System chapter.
Altera Corporation
Signal Name
dbg_rst_n
tap_cold_
rst_n
nTRST pin
dbg_rst_n
on page 3-1
on page 24-1
Description
CTM reset signal. It resets all signals clocked by
CTMCLK.
True power on reset signal to the DAP SWJ-DP. It
must only reset at power-on.
Resets the DAP TAP controller inside the SWJ-DP.
This signal is driven by the host using the JTAG
connector.
Reset signal for TPIU. Resets all registers in the
TRACECLKIN domain.
on page 1-1
cv_54007
2013.12.30
CoreSight Debug and Trace
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