Coresight Debug And Trace Block Diagram And System Integration; Functional Description Of Coresight Debug And Trace - Altera Cyclone V Device Handbook

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2013.12.30

CoreSight Debug and Trace Block Diagram and System Integration

Figure 7-1: HPS CoreSight Debug and Trace System Block Diagram

Functional Description of CoreSight Debug and Trace

CoreSight systems provide all the infrastructure you require to debug, monitor, and optimize the performance
of a complete HPS design. CoreSight technology addresses the requirement for a multicore debug and trace
solution with high bandwidth for whole systems beyond the processor core.
CoreSight Debug and Trace
Send Feedback
PTM-0 ATB
PTM-1 ATB
To DMA
Hardware Events
[31:4]
L3 Interconnect Main Switch
L3 Interconnect
Master Peripheral Switch
HPS Debug
Configuration ROM
System AHB
System APB
DAP
HPS JTAG Pins
Debug
APB
Triggers to/from NOC
Timestamp
Generator
PTM-0 ATB
CoreSight Debug and Trace Block Diagram and System Integration
Funnel
On-Chip
0
Trace RAM
1
2
ATB ATB
3
ETF
.
STM
.
.
[3:0]
7
Replicator
ATB ATB
ETR TPIU
Debug APB
I[3:2]
O[1:0] O[3:2]
csCTI
I[7:4] I[1:0]
O[5:4] O[7:6]
0
CTI-NOC csCTM
3
2
1
Debug APB
4
CTM 1
0
CTI-0
PTM-0 A9-0
HPS Debug System
Hardware Events
CTI Triggers
To Trace Pins [7:0]
Output Trace [31:0]
FPGA-
CTI
MPU Debug Subsystem
MPU Debug
Configuration
ROM
CTI-1
PTM-1 ATB
A9-1 PTM-1
7-3
Events
from FPGA
To Pin
Multiplexer &
Trace Pins
To FPGA
To FPGA
Triggers
to/from
FPGA
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