Guideline: Consider Power-Up State And Memory Initialization - Altera Cyclone V Device Handbook

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Guideline: Consider Power-Up State and Memory Initialization

Figure 2-5: Mixed-Port Read-During-Write: Don t Care or Constrained Don t Care Mode
This figure shows a sample functional waveform of mixed-port read-during-write behavior for the "don't
care" or "constrained don't care" mode.
In the dual-port RAM mode, the mixed-port read-during-write operation is supported if the input registers
have the same clock. The output value during the operation is "unknown."
Related Information
Internal Memory (RAM and ROM) User Guide
Provides more information about the RAM megafunction that controls the read-during-write behavior.
Guideline: Consider Power-Up State and Memory Initialization
Consider the power up state of the different types of memory blocks if you are designing logic that evaluates
the initial power-up values, as listed in the following table.
Table 2-4: Initial Power-Up Values of Embedded Memory Blocks
Memory Type
MLAB
M10K
By default, the Quartus II software initializes the RAM cells in Cyclone V devices to zero unless you specify
a .mif.
All memory blocks support initialization with a .mif. You can create .mif files in the Quartus II software
and specify their use with the RAM megafunction when you instantiate a memory in your design. Even if a
memory is pre-initialized (for example, using a .mif), it still powers up with its output cleared.
Altera Corporation
clk_a&b
wren_a
address_a
data_a
AAAA
byteena_a
11
rden_b
address_b
q_b (asynch)
A0
BBBB CCCC DDDD
01 10
A0
XXXX (unknown data)
Output Registers
Used
Bypassed
Used
Bypassed
Embedded Memory Blocks in Cyclone V Devices
A1
EEEE FFFF
11
A1
Power Up Value
Zero (cleared)
Read memory contents
Zero (cleared)
Zero (cleared)
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