Debug Clocks - Altera Cyclone V Device Handbook

7-16

Debug Clocks

A particular soft logic signal in the FPGA connected to a trigger input in the FPGA-CTI can be configured
to trigger a flush of trace data to the TPIU. For example, you can configure channel 0 to trigger output 2 in
csCTI. Then configure trigger input T3 to channel 0 in FPGA-CTI. Trace data is flushed to the TPIU when
a trigger is received at trigger output 2 in csCTI.
Another soft logic signal in the FPGA connected to trigger input T2 in FPGA-CTI can be configured to
trigger an STM message. csCTI output triggers 4 and 5 are wired to the STM CoreSight component in the
HPS. For example, configure channel 1 to trigger output 4 in csCTI. Then configure trigger input T2 to
channel 1 in FPGA-CTI.
Another soft logic signal in the FPGA fabric connected to trigger input T1 in FPGA-CTI can be configured
to trigger a breakpoint on CPU 1. Trigger output 1 in CTI-1 is wired to the debug request (EDBGRQ) signal
of CPU-1. For example, configure channel 2 to trigger output 1 in CTI-1. Then configure trigger input T1
to channel 2 in FPGA-CTI.
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Debug Clocks
The CoreSight system uses several different clocks. Port Name is the name of the clock signal inputs described
for individual CoreSight debug components in the ARM documentation. Signal Name is the name of the
clock signal used with other HPS components.
Table 7-11: CoreSight Clocks
Port Name
ATCLK
CTICLK(for csCTI)
CTICLK (for FPGA-
CTI)
CTICLK (for CTI-0
and CTI-1)
CTMCLK(for csCTM)
CTMCLK(for CTM)
DAPCLK
PCLKDBG
Altera Corporation
Clock Source Signal Name
Clock
dbg_at_clk
manager
Clock
dbg_at_clk
manager
FPGA fabric
fpga_cti_clk
Clock
mpu_clk
manager
Clock
dbg_clk
manager
Clock
mpu_clk
manager
Clock
dbg_clk
manager
Clock
dbg_clk
manager
Description
Trace bus clock.
Cross trigger interface clock for csCTI. It
can be synchronous or asynchronous to
CTMCLK.
Cross trigger interface clock for FPGA-CTI.
Cross trigger interface clock for CTI-0 and
CTI-1. It can be synchronous or
asynchronous to CTMCLK.
Cross trigger matrix clock for csCTM. It
can be synchronous or asynchronous to
CTICLK.
Cross trigger matrix clock for CTM. It can
be synchronous or asynchronous to
CTICLK.
DAP internal clock. It must be equivalent
to PCLKDBG.
Debug APB (DAPB) clock.
CoreSight Debug and Trace
cv_54007
2013.12.30
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