Resets - Altera Cyclone V Device Handbook

cv_54002
2013.12.30
Table 2-8: Flash Controller Clocks
System Clock Name
qspi_clk
nand_x_clk
nand_clk
sdmmc_clk

Resets

Cold Reset
Cold reset places the hardware-managed clocks into safe mode, the software-managed clocks into their
default state, and asynchronously resets all registers in the clock manager.
Related Information
Safe Mode
Warm Reset
Registers in the clock manager control how the clock manager responds to warm reset. Typically, software
places the clock manager into a safe state in order to generate a known set of clocks for the ROM code to
boot the system. The behavior of the system on warm reset as a whole, including how the FPGA fabric, boot
code, and debug systems are configured to behave, must be carefully considered when choosing how the
clock manager responds to warm reset.
The reset manager can request that the clock manager go into safe mode as part of the reset manager's warm
reset sequence. Before asserting safe mode to the clock manager, the reset manager ensures that the reset
signal is asserted on all modules that receive warm reset.
Clock Manager
Send Feedback
Freq
uency
Up to 432 MHz
Up to 250 MHz
nand_x_clk/4
Up to 200 MHz
on page 2-16
Divided From
Peripheral PLL C2, main
PLL C3, or f2h_periph_
ref_clk
Peripheral PLL C3, main
PLL C4, or f2h_periph_
ref_clk
Peripheral PLL C3, main
PLL C4, or f2h_periph_
ref_clk
Peripheral PLL C3, main
PLL C4, or f2h_periph_
ref_clk
2-15
Resets
Constraints and Notes
Clock for quad SPI,
typically 108 and
80 MHz
NAND flash controller
master and slave clock
Main clock for NAND
flash controller, sets base
frequency for NAND
transactions
• Less than or equal to
memory maximum
operating frequency
• 45% to 55% duty
cycle
• Typical frequencies
are 26 and 52 MHz
• SD/MMC has a
subclock tree divided
down from this clock
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