Serializer Bypass For Ddr And Sdr Operations - Altera Cyclone V Device Handbook

5-64
Transmitter Clocking
Transmitter Clocking
The fractional PLL generates the parallel clocks (rx_outclock and tx_outclock), the load enable (
signal and the
diffioclk
You can statically set the serialization factor to x4, x5, x6, x7, x8, x9, or x10 using the Quartus II software.
The load enable signal is derived from the serialization factor setting.
You can configure any Cyclone V transmitter data channel to generate a source-synchronous transmitter
clock output. This flexibility allows the placement of the output clock near the data outputs to simplify board
layout and reduce clock-to-data skew.
Different applications often require specific clock-to-data alignments or specific data-rate-to-clock-rate
factors. You can specify these settings statically in the Quartus II MegaWizard Plug-In Manager:
The transmitter can output a clock signal at the same rate as the data—with a maximum output clock
frequency that each speed grade of the device supports.
You can divide the output clock by a factor of 1, 2, 4, 6, 8, or 10, depending on the serialization factor.
You can set the phase of the clock in relation to the data using internal PLL option of the ALTLVDS
megafunction. The fractional PLLs provide additional support for other phase shifts in 45° increments.
The following figure shows the transmitter in clock output mode. In clock output mode, you can use an
LVDS channel as a clock output channel.
Figure 5-36: Transmitter in Clock Output Mode
Related Information
Guideline: Use PLLs in Integer PLL Mode for LVDS

Serializer Bypass for DDR and SDR Operations

You can bypass the serializer to support DDR (x2) and SDR (x1) operations to achieve a serialization factor
of 2 and 1, respectively. The I/O element (IOE) contains two data output registers that can each operate in
either DDR or SDR mode.
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signal (the clock running at serial data rate) that clocks the load and shift registers.
Transmitter Circuit
Parallel
FPGA
Fabric
diffioclk
Fractional
PLL
LVDS_LOAD_EN
Series
on page 5-12
LVDS_LOAD_EN
Txclkout+
Txclkout–
I/O Features in Cyclone V Devices
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2014.01.10
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