Stm Channels - Altera Cyclone V Device Handbook

cv_54007
2013.12.30
ROM Entry
0x9
A host debugger can access this table at 0x8000_0000 through the DAP. HPS masters can access this ROM
at 0xFF00_0000. Registers for a particular CoreSight component are accessed by adding the register offset
to the CoreSight component base address, and adding that total to the base address of the ROM table.
The base address of the ROM table is different when accessed from the debugger (at 0x8000_0000) than
when accessed from any HPS master (at 0xFF00_0000). For example, the CTI output enable register,
CTIOUTEN[2] at offset 0xA8, can be accessed by the host debugger at 0x8000_20A8. To derive that value,
add the host debugger access address to the ROM table of 0x8000_0000, to the CTI component base address
of 0x0000_2000, to the CTIOUTEN[2] register offset of 0xA8.

STM Channels

The STM AXI slave is connected to the MPU, DMA, and FPGA-to-HPS bridge masters. Each master has
up to 65536 channels where each channel occupies 256 bytes of address space, for a total of 16 MB per master.
The HPS address map allocates 48 MB of consecutive address space to the STM AXI slave port, divided in
three 16 MB segments.
Table 7-2: STM AXI Slave Port Address Allocation
Segment
0
1
2
Each of the three masters can access any one of the three address segments. Your software design determines
which master uses which segment, based on the value of bits 24 and 25 in the write address,
AWADDRS[25:24]. Software must restrict each master to use only one of the three segments.
Table 7-3: STM AXI Address Fields
AXI Signal Fields
AWADDRS[7:0]
AWADDRS[23:8]
AWADDRS[25:24]
AWADDRS[31:26]
Each STM message contains a master ID that tells the host debugger which master is associated with the
message. The STM master ID is determined by combining a portion of the AWADDRS signal and the AWPROT
protection bit.
CoreSight Debug and Trace
Send Feedback
Offset[30:12]
Start Address
0xFC00_0000
0xFD00_0000
0xFE00_0000
These bits index the 256 bytes of the stimulus port.
These bits identify the 65536 stimulus ports associated with a master.
These bits identify the three masters. Only 0, 1, and 2 are valid values.
Always 0x3F. Bits 24 to 31 combine to access 0xFC00_0000 through 0xFEFF_
FFFF.
0x00000
Description
STM Channels
Description
End of ROM
End Address
0xFCFF_FFFF
0xFDFF_FFFF
0xFEFF_FFFF
Altera Corporation
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