Trace Funnel; Embedded Trace Fifo (Etf); Amba Trace Bus Replicator (Replicator); Embedded Trace Router (Etr) - Altera Cyclone V Device Handbook

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2013.12.30
Related Information
Info center
For more information, refer to the CoreSight System Trace Macrocell Technical Reference Manual on the
ARM info center website.

Trace Funnel

The Trace Funnel multiplexes three trace sources into a single trace stream. Port 0 of the Trace Funnel is
connected to the PTM for CPU 0. Port 1 of the Trace Funnel is connected to the PTM for CPU 1. Port 3 of
the Trace Funnel is connected to the STM. Port 2 and Port 4 through Port 7 are not used.
Related Information
Info center
For more information, refer to the CoreSight Components Technical Reference Manual on the ARM info
center website.

Embedded Trace FIFO (ETF)

The output of the Trace Funnel is sent to the ETF. The ETF is used as an elastic buffer between trace generators
(STM, PTM) and trace destinations. The ETF stores up to 32 KB of trace data in the on-chip trace RAM.

AMBA Trace Bus Replicator (Replicator)

The Replicator broadcasts trace data from the ETF to the embedded trace router (ETR) and trace port
interface unit (TPIU).
Related Information
Info center
For more information, refer to the CoreSight Components Technical Reference Manual on the ARM info
center website.

Embedded Trace Router (ETR)

The ETR can route trace data to the HPS on-chip RAM, the HPS SDRAM, and any memory in the FPGA
fabric connected to the HPS-to-FPGA bridge. The ETR receives trace data from the Replicator. By default,
the buffer to receive the trace data resides in SDRAM at offset 0x00100000 and is 32 KB. You can override
this default configuration by programming registers in the ETR.

Trace Port Interface Unit (TPIU)

The TPIU is a bridge between on-chip trace sources and an off-chip trace port. The TPIU receives trace data
from the Replicator and drives the trace data to a trace port analyzer.
The trace output from the TPIU is software programmable and can be set to either 8 or 32 bits wide. The
trace output is routed to an 8-bit HPS I/O interface and a 32-bit interface to the FPGA fabric. The trace data
sent to the FPGA fabric can be transported off-chip using available serializer/deserializer (SERDES) resources
in the FPGA.
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