Indirect Access Mode - Altera Cyclone V Device Handbook

12-4

Indirect Access Mode

Figure 12-2: Data Slave Remapping Example
To remap the data slave to access other 1 MB regions of the flash device, enable address remapping in the
®
enable ARM AMBA
cfg register. All incoming data slave accesses remap to the offset specified in the remap address register
(remapaddr).
The 20 LSBs of incoming addresses are used for accessing the 1 MB region and the higher bits are ignored.
Note: The quad SPI controller does not issue any error status for accesses that lie outside the connected
flash memory space.
Indirect Access Mode
In indirect access mode, flash data is temporarily buffered in the quad SPI controller's static RAM (SRAM).
Software controls and triggers indirect accesses through the register slave interface. The controller transfers
data through the data slave interface.
Indirect Read Operation
An indirect read operation reads data from the flash memory, places the data into the SRAM, and transfers
the data to an external master through the data slave interface. The indirect read operations are controlled
by the following registers:
• Indirect read transfer register (indrd)
• Indirect read transfer watermark register (indrdwater)
• Indirect read transfer start address register (indrdstaddr)
• Indirect read transfer number bytes register (indrdcnt)
• Indirect address trigger register (indaddrtrig)
These registers need to be configured prior to issuing indirect read operations. The start address needs to
be defined in the indrdstaddr register and the total number of bytes to be fetched is specified in the
indircnt register. Writing 1 to the start indirect read bit (start) of the indrd register triggers the
indirect read operation from the flash memory to populate the SRAM with the returned data.
To read data from the flash device into the SRAM, an external master issues 32-bit read transactions to the
data slave interface. The address of the read access must be in the indirect address range. You can configure
the indirect address through the indaddrtrig register. The external master can issue 32-bit reads until
Altera Corporation
Map to Offset
0x00200000
Data
1 MB
Slave
Address Range
Access
Data Slave
®
advanced high speed bus (AHB) address remapping field (enahbremap) of the
Offsets
0x01000000
0x00300000
0x00200000
0x00100000
Map to Offset 0
0x00000000
16-MB Flash Memory
cv_54012
2013.12.30
Quad SPI Flash Controller
Send Feedback