Altera cyclone V Technical Reference page 1604

cv_5v4
2016.10.28
31 30
15 14
MAC_Address16_Low Fields
Bit
31:0
addrlo
MAC_Address17_High
The MAC Address17 High register holds the upper 16 bits of the 18th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address17 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
Module Instance
emac0
emac1
Offset:
0x808
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Ethernet Media Access Controller
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29 28 27 26
13 12 11 10
Name
This field contains the lower 32 bits of the 17th 6-byte
MAC address. The content of this field is undefined
until loaded by software after the initialization
process.
0xFF700000
0xFF702000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
addrlo
RW 0xFFFFFFFF
9 8 7 6
addrlo
RW 0xFFFFFFFF
Description
Base Address
MAC_Address17_High
21 20 19 18
5 4 3 2
Access
Register Address
0xFF700808
0xFF702808
17-389
17 16
1 0
Reset
RW 0xFFFFF
FFF
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