Quad Spi Flash Controller Programming Model; Setting Up The Quad Spi Flash Controller; Indirect Read Operation With Dma Disabled - Altera Cyclone V Device Handbook

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Quad SPI Flash Controller Programming Model

Quad SPI Flash Controller Programming Model

Setting Up the Quad SPI Flash Controller

The following steps describe how to set up the quad SPI controller:
1. Wait until any pending operation has completed.
2. Disable the quad SPI controller with the quad SPI enable field (en) of the cfg register.
3. Update the instwidth field of the devrd register with the instruction type you wish to use for indirect
and direct writes and reads.
4. If mode bit enable bit (enmodebits) of the devrd register is enabled, update the mode bit register
(modebit).
5. Update the devsz register as needed. Parts or all of this register might have been updated after initial-
ization. The number of address bytes is a key configuration setting required for performing reads and
writes. The number of bytes per page is required for performing any write. The number of bytes per
device block is only required if the write protect feature is used.
6. Update the device delay register (delay). This register allows the user to adjust how the chip select is
driven after each flash access. Each device may have different timing requirements. If the serial clock
frequency is increased, these timing requirements become more critical. The numbers specified in this
register are based on the period of the l4_main_clk clock. For example, an some devices need 50 ns
minimum time before the slave select can be reasserted after it has been deasserted. When the device is
operating at 100 MHz, the clock period is 10 ns, so 40 ns extra is required. If the l4_main_clk clock
is running at 400 MHz (2.5 ns period), specify a value of at least 16 to the clock delay for chip select
deassert field (nss) of the delay register.
7. Update the remapaddr register as needed. This register only affects direct access mode.
8. Set up and enable the write protection registers (wrprot, lowwrprot, and uppwrprot), when write
protection is required.
9. Enable required interrupts though the irqmask register.
10. Set up the bauddiv field of the cfg register to define the required clock frequency of the target device.
11. Update the read data capture register (rddatacap) as needed. This register delays when the read data
is captured and can help when the read data path from the device to the quad SPI controller is long and
the device clock frequency is high.
12. Enable the quad SPI controller with the en field of the cfg register.

Indirect Read Operation with DMA Disabled

The following steps describe the general software flow to set up the quad SPI controller for indirect read
operation with the DMA disabled:
1. Perform the steps described in the Setting Up the Quad SPI Flash Controller" section.
2. Set the flash memory start address in the indrdstaddr register.
3. Set the number of bytes to be transferred in the indrdcnt register.
4. Set the indirect transfer trigger address in the indaddrtrig register.
5. Set up the required interrupts through the irqmask register.
6. If the watermark level is used, set the SRAM watermark level through the indrdwater register.
7. Start the indirect read operation by setting the start field of the indrd register to 1.
Altera Corporation
cv_54012
2013.12.30
Quad SPI Flash Controller
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