Xip Mode - Altera Cyclone V Device Handbook

12-10

XIP Mode

Instruction Lanes Used By
Opcode
Dual 2
command
fast read
(DCFR)
Quad 4
command
fast read
(QCFR)
Table 12-2: Quad SPI Configuration for Micron N25Q128 Device (Write Instructions)
Instruction
Page program 1
Dual input fast 1
program (DIFP)
Dual input 1
extended fast
program
(DIEFP)
Quad input fast 1
program (QIFP)
Quad input 1
extended fast
program
(QIEFP)
Dual command 2
fast program
(DCFP)
Quad command 4
fast program
(QCFP)
XIP Mode
The quad SPI controller supports XIP mode, if the flash devices support XIP mode. Depending on the flash
device, XIP mode puts the flash device in read-only mode, reducing command overhead.
The quad SPI controller must instruct the flash device to enter XIP mode by sending the mode bits. When
the enter XIP mode on next read bit (enterxipnextrd) of the cfg register is set to 1, the quad SPI
controller and the flash device are ready to enter XIP mode on the next read instruction. When the enter
XIP mode immediately bit (enterxipimm) of the cfg register is set to 1, the quad SPI controller and flash
device enter XIP mode immediately.
When the enterxipnextrd or enterxipimm bit of the cfg register is set to 0, the quad SPI controller
and flash device exit XIP mode on the next read instruction. For more information, refer to the XIP Mode
Operations" section.
Altera Corporation
Lanes Used to
Send Address
2
4
Lanes Used Lanes Used to
By Opcode Send Address
1
1
2
1
4
2
4
Lanes Used to instwidth Value
Send Data
2 1
4 2
Lanes Used to instwidth
Send Data Value
1 0
2 0
2 0
4 0
4 0
2 1
4 2
addrwidth datawidth
Value
Don't care Don't care
Don't care Don't care
addrwidth datawidth Value
Value
0 0
0 1
1 1
0 2
2 2
Don't care Don't care
Don't care Don't care
Quad SPI Flash Controller
Send Feedback
cv_54012
2013.12.30
Value