Quad Spi Flash Controller Address Map And Register Definitions; Document Revision History - Altera Cyclone V Device Handbook

12-18
XIP Mode at Power on Reset
3. Set the enterxipnextrd bit of the cfg register to 0.
The flash device must receive a read instruction before it can disable its internal XIP mode state.
Thus, XIP mode internally stays active until the next read instruction is serviced. Ensure that XIP
mode is disabled before the end of any read sequence.
XIP Mode at Power on Reset
Some flash devices can be XIP-enabled as a nonvolatile configuration setting, allowing the flash device to
enter XIP mode at power-on reset (POR) without software intervention. Software cannot discover the XIP
state at POR through flash status register reads because an XIP-enabled flash device can only be accessed
through the XIP read operation. If you known the device will enter XIP mode at POR, have your initial boot
software configure the modebit register and set the enterxipimm bit of the cfg register to 1.
If you do not known in advance whether or not the device will enter XIP mode at POR, have your initial
boot software issue an XIP mode exit command through the flashcmd register, then follow the steps in
the Entering XIP Mode" section. Software must be aware of the mode bit requirements of the device, because
XIP mode entry and exit varies by device.
Related Information
Entering XIP Mode

Quad SPI Flash Controller Address Map and Register Definitions

The address map and register definitions reside in the Address Map Information for Cyclone V SoC HPS
file that accompanies this handbook volume. Click the link, below, to open the file.
To view the module description and base address, scroll to and click the following links for the module
instance:
• qspiregs
• qspidata
To then view the register and field descriptions, scroll to and click the register names. The register addresses
are offsets relative to the base address of each module instance.
Related Information
• Introduction to Cyclone V Hard Processor System (HPS)
• Cyclone V SoC HPS Address Map and Register Definitions

Document Revision History

Table 12–4 shows the revision history for this document.
Table 12-5: Document Revision History
Date
December 2013
Altera Corporation
on page 12-16
2013.12.30
on page 1-1
Version
Maintenance release
cv_54012
2013.12.30
Changes
Quad SPI Flash Controller
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