Indirect Read Operation With Dma Enabled; Indirect Write Operation With Dma Disabled - Altera Cyclone V Device Handbook

cv_54012
2013.12.30
8. Either use the watermark level interrupt or poll the SRAM fill level in the sramfill register to determine
when there is sufficient data in the SRAM.
9. Issue a read transaction to the indirect address to access the SRAM. Repeat
are needed to complete the indirect read transfer.
10. Either use the indirect complete interrupt to determine when the indirect read operation has completed
or poll the completion status of the indirect read operation through the indirect completion status bit
(ind_ops_done_status) of the indrd register.
Related Information
Setting Up the Quad SPI Flash Controller

Indirect Read Operation with DMA Enabled

The following steps describe the general software flow to set up the quad SPI controller for indirect read
operation with the DMA enabled:
1. Perform the steps described in the Setting Up the Quad SPI Flash Controller" section.
2. Set the flash memory start address in the indrdstaddr register.
3. Set the number of bytes to be transferred in the indrdcnt register.
4. Set the indirect transfer trigger address in the indaddrtrig register.
5. Set the number of bytes for single and burst type DMA transfers in the dmaper register.
6. Optionally set the SRAM watermark level in the indrdwater register to control the rate DMA requests
are issued.
7. Start an indirect read access by setting the start field of the indrd register to 1.
8. Either use the indirect complete interrupt to determine when the indirect read operation has completed
or poll the completion status of the indirect read operation through the ind_ops_done_status field
of the indrd register.
Related Information
Setting Up the Quad SPI Flash Controller

Indirect Write Operation with DMA Disabled

The following steps describe the general software flow to set up the quad SPI controller for indirect write
operation with the DMA disabled:
1. Perform the steps described in the Setting Up the Quad SPI Flash Controller" section.
2. Set the flash memory start address in the indwrstaddr register.
3. Set up the number of bytes to be transferred in the indwrcnt register.
4. Set the indirect transfer trigger address in the indaddrtrig register.
5. Set up the required interrupts through the interrupt mask register (irqmask).
6. Optionally set the SRAM watermark level in the indwrwater register to control the rate DMA requests
are issued. The value set must be greater than one flash page. For more information, refer to the Indirect
Write Operation" section.
7. Start the indirect write operation by setting the start field of the indwr register to 1.
8. Either use the watermark level interrupt or poll the SRAM fill level in the sramfill register to determine
when there is sufficient space in the SRAM.
Quad SPI Flash Controller
Send Feedback
Indirect Read Operation with DMA Enabled
on page 12-14
on page 12-14
12-15
step 8 if more read transactions
Altera Corporation