Integrating The Qsys System Into The Quartus Ii Project; Developing Software With The Nios Ii Software Build Tools For Eclipse - Altera Nios II Hardware Development Manual

1–6
f
For more information about the following topics, refer to the related documentation:
■ For Nios II processor cores, refer to the
■ For Qsys and developing custom components, refer to the System Design with Qsys
section of
For custom instructions, refer to the
■

Integrating the Qsys System into the Quartus II Project

After generating the Nios II system using Qsys, you integrate it into the Quartus II
project. Using the Quartus II software, you perform all tasks required to create the
final FPGA hardware design.
As shown in
Nios II system. You can integrate your own custom hardware modules into the FPGA
design, or you can integrate other ready-made intellectual property (IP) design
modules available from Altera or third party IP providers. This tutorial does not cover
adding other logic outside the Nios II system.
Using the Quartus II software, you also assign pin locations for I/O signals, specify
timing requirements, and apply other design constraints. Finally, you compile the
Quartus II project to produce a .sof to configure the FPGA.
You download the .sof to the FPGA on the target board using an Altera download
cable, such as the USB-Blaster. After configuration, the FPGA behaves as specified by
the hardware design, which in this case is a Nios II processor system.
f
For further information about using the Quartus II software, refer to
Quartus II
Tutorial in the

Developing Software with the Nios II Software Build Tools for Eclipse

Using the Nios II Software Build Tools (SBT) for Eclipse™, you perform all software
development tasks for your Nios II processor system. After you generate the system
with Qsys, you can begin designing your C/C++ application code immediately with
the Nios II SBT for Eclipse. Altera provides component drivers and a hardware
abstraction layer (HAL) which allows you to write Nios II programs quickly and
independently of the low-level hardware details. In addition to your application code,
you can design and reuse custom libraries in your Nios II SBT for Eclipse projects.
To create a new Nios II C/C++ application project, the Nios II SBT for Eclipse uses
information from the .sopcinfo file. You also need the .sof file to configure the FPGA
before running and debugging the application project on target hardware.
The Nios II SBT for Eclipse can produce several outputs, listed below. Not all projects
require all of these outputs.
■ system.h file—Defines symbols for referencing the hardware in the system. The
Nios II SBT for Eclipse automatically create this file when you create a new board
support package (BSP).
■ Executable and Linking Format File (.elf)—Is the result of compiling a C/C++
application project, that you can download directly to the Nios II processor.
Nios II Hardware Development Tutorial
Volume 1: Design and Synthesis
Figure 1–1 on page 1–2, most FPGA designs include logic outside the
Software, the Quartus II Handbook, and the Quartus II Software Interactive
Training Courses section of the Altera website.
Chapter 1: Nios II Hardware Development
Nios II System Development Flow
Nios II Processor Reference
of the Quartus II Handbook.
Nios II Custom Instruction User
May 2011 Altera Corporation
Handbook.
Guide.
Introduction to the