Card Read Threshold - Altera Cyclone V Device Handbook

cv_54011
2013.12.30
• cmd register setting: data_expected bit set to 0
• cmdarg register settings:
• Bit [31] set to 1
• Bits [7:2] set to 4
• All other bits set to 0
• Task file settings:
• Command field of the ATA task file set to 0xE0
• Reserved fields of the task file set to 0
• bytcnt register and block_size field of the blksiz register: set to 16
The FLUSH CACHE EXT Command
For card devices that buffer/cache written data, the FLUSH CACHE EXT command ensures that buffered
data is written to the card media. For cards that do not buffer written data, the FLUSH CACHE EXT command
returns a success status. No data transfer (RW_BLK) is expected for this ATA command.
The host issues a RW_REG command for the ATA command, and the status is retrieved with the SD/SDIO
CMD39 or RW_REG command. There can be error status for this ATA command, in which case fields other
than the status field of the ATA task file are valid.
The host controller uses the following settings while sending the RW_REG command for the STANDBY
IMMEDIATE ATA command:
• cmd register setting: data_expected bit set to 0
• cmdarg register settings:
• Bit [31] set to 1
• Bits [7:2] set to 4
• All other bits set to 0
• Task file settings:
• Command field of the ATA task file set to 0xEA
• Reserved fields of the task file set to 0
• bytcnt register and block_size field of the blksiz register: set to 16

Card Read Threshold

When an application needs to perform a single or multiple block read command, the application must set
the cardthrctl register with the appropriate card read threshold size in the card read threshold field
(cardrdthreshold) and set the cardrdthren bit to 1. This additional information specified in the
controller ensures that the controller sends a read command only if there is space equal to the card read
threshold available in the RX FIFO buffer. This in turn ensures that the card clock is not stopped in the
middle a block of data being transmitted from the card. Set the card read threshold to the block size of the
transfer to guarantee there is a minimum of one block size of space in the RX FIFO buffer before the controller
enables the card clock.
The card read threshold is required when the round trip delay is greater than half of sdmmc_clk_divided.
SD/MMC Controller
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The FLUSH CACHE EXT Command
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