On-Chip Ram Block Diagram And System Integration; Functional Description Of The On-Chip Ram - Altera Cyclone V Device Handbook

9-2

On-Chip RAM Block Diagram and System Integration

On-Chip RAM Block Diagram and System Integration
Transfers between memory and the NIC-301 L3 interconnect happen through a 64-bit interface, gated by
the l3_main_clk interconnect clock. ECC logic detects single-bit, corrected and double-bit, uncorrected
errors. The memory has a read acceptance of two, a write acceptance of two, and a total acceptance of two
wit round-robin arbitration.
The entire RAM is either secure or nonsecure. Security is enforced by the NIC-301 L3 interconnect.
Figure 9-1: On-Chip RAM Block Diagram
Note: You must initialize the on-chip RAM before you enable the ECC support to prevent false ECC
interrupts triggered by uninitialized bits.
Related Information
Interconnect on page 4-1
For more information about security, refer to the Interconnect chapter.

Functional Description of the On-Chip RAM

The on-chip RAM serves as a general-purpose memory accessible from the FPGA.
The on-chip RAM uses an 64-bit slave interface. The slave interface supports transfers between memory
and the NIC-301 L3 interconnect. All reads and writes are serviced in order.
Clocks
The on-chip RAM is driven by the l3_main_clk interconnect clock.
Resets
The contents of the RAM remain unchanged on a cold or warm reset. Reset only clears the state associated
with the slave interface.
The on-chip RAM reset is driven by the onchip_ram_rst_n interconnect reset signal.
Related Information
• Clock Manager
For more information about the operating frequency and maximum throughput, refer to the Clock
Manager chapter.
• Reset Manager
Altera Corporation
NIC-301
L3 Interconnect
Data Interface
M
ECC Register Interface
on page 2-1
on page 3-1
On-Chip RAM
S
ECC from System Manager
ECC Interrupts
to System Manager
On-Chip Memory
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2013.12.30