Controller/Dma/Fifo Buffer Reset Usage; Enabling Fifo Buffer Ecc - Altera Cyclone V Device Handbook

cv_54011
2013.12.30
You can also use the clkena register to enable low-power mode, which automatically stops the
sdmmc_cclk_out clock when the card is idle for more than eight clock cycles.
Related Information
Interrupt and Error Handling
Refer to this section for information about hardware lock errors.

Controller/DMA/FIFO Buffer Reset Usage

The following list shows the effect of reset on various parts in the SD/MMC controller:
• Controller reset resets the controller by setting the controller_reset bit in the ctrl register to
1. Controller reset resets the CIU and state machines, and also resets the BIU-to-CIU interface. Because
this reset bit is self-clearing, after issuing the reset, wait until this bit changes to 0.
• FIFO buffer reset resets the FIFO buffer by setting the FIFO reset bit (fifo_reset) in the ctrl
register to 1. FIFO buffer reset resets the FIFO buffer pointers and counters in the FIFO buffer. Because
this reset bit is self-clearing, after issuing the reset, wait until this bit changes to 0.
• DMA reset resets the internal DMA controller logic by setting the DMA reset bit (dma_reset) in the
ctrl register to 1, which immediately terminates any DMA transfer in progress. Because this reset bit
is self-clearing, after issuing the reset, wait until this bit changes to 0.
Note: Ensure that the DMA is idle before performing a DMA reset. Otherwise, the L3 interconnect might
be left in an indeterminate state.
Altera recommends setting the controller_reset, fifo_reset, and dma_reset bits in the ctrl
register to 1 first, and then resetting the rintsts register to 0 using another write, to clear any resultant
interrupt.

Enabling FIFO Buffer ECC

To protect the FIFO buffer data with ECC, you must enable the ECC feature before performing any operations
with the SD/MMC controller. Perform the following steps to enable the FIFO buffer ECC feature:
1. Verify there are no commands committed to the controller.
2. Ensure that the FIFO buffer is initialized. Initialize the FIFO buffer by writing 0 to all 1024 FIFO buffer
locations. A FIFO buffer write to any address from 0x200 to the maximum FIFO buffer size is valid.
3. Set the SDMMC RAM ECC single and double, correctable error interrupt status bits (serrporta,
derrporta, serrportb, and derrportb) to 1 in the sdmmc register in the eccgrp group of the
system manager, to clear any previously-detected ECC errors.
4. Reset the FIFO buffer by setting the fifo_reset bit to 1 in the ctrl register. This action resets
pointers and counters in the FIFO buffer. This reset bit is self-clearing, so after issuing the reset, wait
until the bit changes to 0.
5. Set the en bit in sdmmc register in eccgrp group of the system manager to 1, to enable ECC for the
FIFO buffer in SD/MMC controller.
Non-Data Transfer Commands
To send any non-data transfer command, the software needs to write the cmd register and the cmdarg
register with appropriate parameters. Using these two registers, the controller forms the command and sends
it to the CMD pin. The controller reports errors in the command response through the error bits of the
rintsts register.
SD/MMC Controller
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on page 11-60
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Controller/DMA/FIFO Buffer Reset Usage
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