Local Memory Buffer - Altera Cyclone V Device Handbook

12-6
Consecutive Reads and Writes
write to complete the transfer. If there are less than four bytes of data to write on the last transfer, the external
master can still issue a 32-bit write and the quad SPI controller discards the extra bytes.
The SRAM size can limit the amount of data that the quad SPI controller can accept from the external master.
If the SRAM is not full at the point of the write access, the data is pushed to the SRAM with minimum latency.
If the external master attempts to push more data to the SRAM than the SRAM can accept, the quad SPI
controller backpressures the external master with wait states. When the SRAM resource is freed up by pushing
the data from SRAM to the flash memory, the SRAM is ready to receive more data from the external master.
When the SRAM holds an equal or greater number of bytes than the size of a flash page, or when the SRAM
holds all the remaining bytes of the current indirect transfer, the quad SPI controller initiates a write operation
to the flash memory.
The processor can also use the SRAM fill level, in the sramfill register, to control when to write more
data into the SRAM.
Alternatively, you can configure the fill level watermark of the SRAM in the indwrwater register. When
the SRAM fill level falls below the watermark level, an indirect transfer watermark interrupt is generated to
tell software to write the next page of data to SRAM. Because the quad SPI controller initiates non-end-of-
data writes to the flash memory only when the SRAM contains a full flash page of data, you must set the
watermark level to a value greater than one flash page to avoid the system stalling. You can disable the
watermark feature by writing zero to the indwrwater register.
If the address of the write access is outside the range of the indirect trigger address, one of the following
actions occurs:
• When direct access mode is enabled, the write uses direct access mode.
• When direct access mode is disabled, the slave returns an error back to the requesting master.
You can cancel an indirect operation by setting the cancel indirect write bit (cancel) of the indwr register
to 1. For more information, refer to the Indirect Write Operation with DMA Disabled" section.
Related Information
Indirect Write Operation with DMA Disabled
Consecutive Reads and Writes
It is possible to trigger two indirect operations at a time by triggering the start bit of the indrd or indwr
register twice in short succession. The second operation can be triggered while the first operation is in
progress. For example, software may trigger an indirect read or write operation while an indirect write
operation is in progress. The corresponding start and count registers must be configured properly before
software triggers each transfer operation.
This approach allows for a short turnaround time between the completion of one indirect operation and the
start of a second operation. Any attempt to queue more than two operations causes the indirect read reject
interrupt to be generated.

Local Memory Buffer

The SRAM local memory buffer is a 128 by 32-bit (512 total bytes) memory and includes support for error
correction code (ECC). The ECC logic provides outputs to notify the system manager when single-bit
correctable errors are detected (and corrected) and when double-bit uncorrectable errors are detected. The
ECC logic also allows the injection of single- and double-bit errors for test purposes.
The SRAM has two partitions, with the lower partition reserved for indirect read operations and the upper
partition for indirect write operations, as shown in
SRAM partition register (srampart), based on 32-bit word sizes. For example, to specify four bytes of
storage, write the value 1. The value written to the indirect read partition size field (addr) defines the number
Altera Corporation
on page 12-15
Figure 12-1. The size of the partitions is specified in the
cv_54012
2013.12.30
Quad SPI Flash Controller
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