Configuration By Host - Altera Cyclone V Device Handbook

10-4

Configuration by Host

Register
noinit
page512
noloadb0p0
tworowaddr
Related Information
Configuration by Host
Configuration by Host
If the system manager sets bootstrap_inhibit_init to 1, the NAND flash controller does not perform
the discovery and initialization process. In this case, the host processor must configure the flash controller.
When performance is not a concern in the design, the timing registers can be left unprogrammed.
Related Information
Bootstrap Setting Bits
Recommended configuration-by-host settings to enable the basic read, write, and erase operations for a
single-plane, 512 bytes/page device
Recommended Bootstrap Settings for 512 Byte Page Device
Register
devices_connected
device_width
number_of_planes
device_main_area_size
device_spare_area_size
pages_per_block
NAND Page Main and Spare Areas
Each NAND page has a main area and a spare area. The main area is intended for data storage. The spare
area is intended for ECC and maintenance data, such as wear leveling information. Each block consists of
a group of pages.
(17)
When this register is set, the NAND flash controller expects the host to program the related device parameter
registers. For more information, refer to Configuration by Host.
(18)
All registers are in the config group.
Altera Corporation
(17)
1
1
1
• 1 flash device supports two-cycle addressing
• 0 flash device support three-cycle addressing
on page 10-4
on page 10-3
(18)
1
0 indicating an 8-bit NAND flash device
1 indicating a single-plane device
The value of this register must reflect the flash device's page
main area size.
The value of this register must reflect the flash device's page
spare area size.
The value of this register must reflect number of pages per
block in the flash device.
Value
Value
NAND Flash Controller
Send Feedback
cv_54010
2013.12.30