Bootstrap Interface - Altera Cyclone V Device Handbook

cv_54010
2013.12.30
The NAND flash controller performs the following initialization steps:
1. If the system manager is asserting bootstrap_inhibit_init, the flash controller goes directly to
step 7.
2. When the device is ready, the flash controller sends the ONFI Read ID command to read the ONFI
signature from the device, to determine whether an ONFI or a legacy device is connected.
3. If the data returned by the device has an ONFI signature, the flash controller then reads the device
parameter page. The flash controller stores the relevant device feature information in internal memory
control registers, enabling it to correctly program other registers in the flash device, and goes to step 5.
4. If the data does not have a valid ONFI signature, the flash controller assumes that it is a legacy (non-
ONFI) device. The flash controller then performs the following steps:
a. Sends the reset command to the device
b. Reads the device signature information
c. Stores the relevant values into internal memory controller registers
5. The flash controller resets the device. At the same time, it verifies the width of the memory interface. The
HPS supports one 8-bit NAND flash device. As a result, the flash controller always detects an 8-bit memory
interface.
6. The flash controller sends the Page Load command to block 0, page 0 of the device, configuring direct
read access, so the processor can boot from that page. The processor can start reading from the first page
of the device, which is the expected location of the preloader software.
Note:
7. The flash controller sends the reset command to the device.
8. The flash controller sets the value of the rst_comp bit in the intr_status0 register in the status
group.

Bootstrap Interface

The NAND flash controller provides a bootstrap interface that allows software to override the default behavior
of the flash controller. The bootstrap interface contains four bits, which when set appropriately allow the
flash controller to skip the initialization phase and begin loading from flash memory immediately after reset.
These bits are driven by software through the system manager. They are sampled by the NAND flash controller
when the controller is released from reset.
Related Information
• System Manager
More information about the bootstrap interface control bits.
• System Manager
More information about the bootstrap interface control bits.
Bootstrap Setting Bits
The following table lists the relevant bootstrap setting bits, found in the system manager's bootstrap
register, in the nandgrp group. This table also lists recommended bootstrap settings for a 512 byte page
device.
NAND Flash Controller
Send Feedback
The system manager can bypass this step by asserting bootstrap_inhibit_b0p0_load
before reset is deasserted.
on page 14-1
10-3
Bootstrap Interface
Altera Corporation