Control Register - Analog Devices ADSP-SC58 Series Hardware Reference Manual

Control Register

The controls the clock generation divisors for SYS_CLKIN and the PLL. Read after write accesses to the
CGU_CTL
CGU_CTL register returns the new value even if the clock's frequency change is still in progress.
MSEL (R/W)
Multiplier Select
LOCK (R/W)
Lock
Figure 3-6: CGU_CTL Register Diagram
Table 3-12: CGU_CTL Register Fields
Bit No.
(Access)
31 LOCK
(R/W)
30 WFI
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15 14 13 12 11 10
0 0 0 1 0 0
31 30 29 28 27 26
0 0 0 0 0 0
Bit Name
Lock.
If the global lock bit is set (SPU_CTL.GLCK bit =1) and the CGU_CTL.LOCK bit is
set, the
Wait For Idle.
Modifying the PLL multiplier requires the PLL to re-lock and once the PLL locks,
clocks have to be synchronized. Changes to the CGU_CTL.MSEL and the
CGU_CTL.DF bit values results in bypassing the PLL.
The CGU_CTL.WFI bit forces the PLL to wait for all processor cores to be in an idle
or reset state before changing frequencies as a result of changes to the
CGU_CTL.MSEL or CGU_CTL.DF bits. Write accesses to the
the CGU_CTL.DF or CGU_CTL.MSEL bit values while the PLL is locking sets the
CGU_STAT.WDFMSERR bit.
9 8 7 6 5 4 3 2
0 0 0 0 0 0 0 0
25 24 23 22 21 20 19 18
0 0 0 0 0 0 0 0
Description/Enumeration
register is read only (locked).
CGU_CTL
0 Unlock
1 Lock
0 Update Immediately
1 Wait for Idle
ADSP-SC58x CGU Register Descriptions
1 0
0 0
DF (R/W)
Divide Frequency
17 16
0 0
WFI (R/W)
Wait For Idle
CGU_CTL to change
3–19