Table of Contents
Advertisement
Architectural Concepts
Table 10-8: LPDDR Page Interleaving (Continued)
SDRAM size
Row address bits
2 Gb
27:14
DMC Clocking
The DMC uses a divided-down version of the PLLCLK (PLL clock) to generate an internal clock for clocking the
DMC block and interface. The specific value of the DCLK frequency is programmed in the
section
Initializing the DMC (ADSP-SC58x)
For information on the maximum clock frequency supported for specific modes, refer to the processor data sheet.
For the processor variants that have two DMC blocks, both blocks run on the same DCLK frequency.
NOTE:
NOTE:
In some cases, it might be required to generate a DCLK frequency asynchronous to CCLK (for example,
CCLK=450 MHz and DCLK=400 MHz). For these cases, one CGU can be used to generate CCLK and
another can be used to generate DCLK. For more details, refer to the CGU chapter.
DMC DMA
The DMC supports DMA-based transfers to and from external DDR SDRAM memory and internal memory.
The DMC DMA controller, part of the distributed DMA engines (DDE) that are dispersed through the infrastruc-
ture, connects to the system crossbar fabric.
The DMC uses two DDEs for memory-to-memory DMA (MDMA). One channel is the source channel, and the
second, the destination channel.
DMA transfers on the processor are descriptor-based or register-based. Register-based DMA allows the processor to
program DMA control registers directly to initiate a DMA transfer. On completion, the control registers can be au-
tomatically updated with their original setup values for continuous transfer, if needed. Descriptor-based DMA trans-
fers require a set of parameters stored within memory to initiate a DMA sequence. This transfer allows the chaining
together of multiple DMA sequences. In descriptor-based DMA operations, a DMA channel can be programmed to
set up and start another DMA transfer automatically after the current sequence completes.
Refer to the DMA chapter for further details.
Enhanced DMA operations (such as delay line DMA, scatter or gather DMA) are also supported to or from the
DMC module. For more details, refer to the Extended Memory DMA (EMDMA) chapter.
DMC Operating Modes
By default, the DMC is in DDR2 mode. To enable DDR3 or LPDDR mode, the corresponding bits in the
DMC_CTL
and
DMC_PHY_CTL4
10–12
Bank address bits
13:11
describes the procedure.
register must be configured.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Column address bits
10.1
register. The
CGU_DIV
Advertisement
Table of Contents
