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Channel A Control Register
The
register selects the low and high side output pulse mode, enables low and high side output, and
PWM_ACTL
enables low/high side output crossover.
PULSEMODELO (R/W)
Low Side Output Pulse Position
PULSEMODEHI (R/W)
High Side Output Pulse Position
XOVR (R/W)
high-low Crossover Enable
Figure 19-28: PWM_ACTL Register Diagram
Table 19-6: PWM_ACTL Register Fields
Bit No.
(Access)
11:10
PULSEMODELO
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
9
0
0
0
0
0
0
0
31
30
29
28
27
26
25
0
0
0
0
0
0
0
Bit Name
Low Side Output Pulse Position.
The PWM_ACTL.PULSEMODELO bits select the pulse position for Channel A low
side output. In symmetrical mode, the channel forms a symmetrical pulse waveform
around the center of the PWM period. Only one of the duty cycle registers is used for
an output in symmetrical mode. Note that in this mode, the values in the
register is scaled, such that a value of 0 produces 50% duty. In asymmetrical mode, the
channel forms an asymmetrical pulse waveform around the center of the PWM period.
This mode uses both the duty cycle registers
or right half mode, the channel forms the pulse waveforms on either the first half (left)
or the second half (right) of the PWM period. This mode uses both the duty cycle reg-
isters
(PWM_AL0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
Description/Enumeration
and PWM_AL1).
0 Symmetrical
1 Asymmetrical
2 Left Half
3 Right Half
ADSP-SC58x PWM Register Descriptions
0
0
DISHI (R/W)
Channel High Side Output Disable
DISLO (R/W)
Channel Low Side Output Disable
16
0
(PWM_AL0
and PWM_AL1). In left half
PWM_AL0
19–43
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