Analog Devices ADSP-SC58 Series Hardware Reference Manual page 491

SMC Programmable Timing Characteristics
Figure 11-4: Fast Asynchronous SRAM Reads, Burst of Four Word
In this case, the target SMC bank has been programmed with:
• read setup time = 1 cycle
• read access time = 2 cycles
• read hold time = 0
• SMC_B0ETIM.PREAT = 0
• SMC_B0ETIM.PREST = 0
• IDLE transition time = 0
The SMC_AMS[n] signal is asserted at the start of the setup cycle of the first read out of the burst. Since the hold
time and the idle transition time have been programmed to 0, the SMC_AMS[n] signal does not deassert until the
entire set of reads concludes. Only the SMC_ARE signal deasserts periodically for 1 cycle for the setup period. The
read address changes to the next address at the start of each individual setup cycle. Read data words are latched at the
end of each individual read access period.
High-Speed Asynchronous SRAM Writes
High-speed asynchronous SRAM writes are similar to the high-speed read accesses. The Fast Asynchronous SRAM
Writes figure shows the bus protocol for a write burst of 4 words. Here, the write setup time is 1 cycle and the write
access time has been programmed to 2 cycles. Write hold time, pre-access time, pre-setup time, and idle transition
time are programmed to 0.
The chip select signal SMC_AMS[n] asserts at the start of the entire write burst and deasserts only at the end of the
last individual write access period. Write address, byte enables and write data for each individual write access are
presented onto the bus at the start of each individual write setup cycle. The SMC_AWE signal asserts for the write
access period and deasserts during the setup period for each individual data write.
11–10
Setup Read Access
1 Cycle
CLKOUT
ADDRn A0 A0 + 1
AMSn
AOE
ARE
DATA15-0
D0
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Trans. TURN
2 Cycles
2 Cycles
A0 + 2 A0 + 3
D1 D2 D3
Read Data Latching Edges