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ADSP-SC58x PORT Register Descriptions
Port x GPIO Input Enable Register
The PORT_INEN, PORT_INEN_SET, and
required for using a GPIO pin in input mode.
Writes to the
PORT_INEN
without impacting other pin drivers of the port, use the
If the input is enabled, reads from the PORT_DATA, PORT_DATA_SET, or
the state of the pins. However, the state of the output is not overwritten by the input. It is altered by software writes
only. Input and output drivers can be enabled at the same time. In this case, a read of the data register returns the
true value of the data register and not the pin state.
For more information, see the
PX15 (R/W)
Port x Bit 15 Input Enable
PX14 (R/W)
Port x Bit 14 Input Enable
PX13 (R/W)
Port x Bit 13 Input Enable
PX12 (R/W)
Port x Bit 12 Input Enable
PX11 (R/W)
Port x Bit 11 Input Enable
PX10 (R/W)
Port x Bit 10 Input Enable
PX9 (R/W)
Port x Bit 9 Input Enable
PX8 (R/W)
Port x Bit 8 Input Enable
Figure 14-17: PORT_INEN Register Diagram
Table 14-18: PORT_INEN Register Fields
Bit No.
(Access)
15
PX15
(R/W)
14–48
PORT_INEN_CLR
register affect the input drivers for all pins of the port. To set or clear specific pin drivers
register description and the
PORT_DATA
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
Port x Bit 15 Input Enable.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
registers enable or disable input drivers, which are
PORT_INEN_SET
PORT_DIR
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 Disable Input Driver
1 Enable Input Driver
and
PORT_INEN_CLR
PORT_DATA_CLR
register description.
1
0
0
0
PX0 (R/W)
Port x Bit 0 Input Enable
PX1 (R/W)
Port x Bit 1 Input Enable
PX2 (R/W)
Port x Bit 2 Input Enable
PX3 (R/W)
Port x Bit 3 Input Enable
PX4 (R/W)
Port x Bit 4 Input Enable
PX5 (R/W)
Port x Bit 5 Input Enable
PX6 (R/W)
Port x Bit 6 Input Enable
PX7 (R/W)
Port x Bit 7 Input Enable
17
16
0
0
registers.
registers return
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