Analog Devices ADSP-SC58 Series Hardware Reference Manual page 584

ADSP-SC58x PORT Register Descriptions
Figure 14-6: GPIO Programming Model Flow (Part 3)
ADSP-SC58x PORT Register Descriptions
The General-Purpose Input/Output Port (PORT) contains the following registers.
Table 14-7: ADSP-SC58x PORT Register List
Name
PORT_DATA
PORT_DATA_CLR
PORT_DATA_SET
PORT_DATA_TGL
PORT_DIR
PORT_DIR_CLR
PORT_DIR_SET
PORT_FER
PORT_FER_CLR
PORT_FER_SET
14–12
REGISTER ISR TO REQUIRED EVTX
ASSIGN PINTx TO REQUIRED IVGX
UNMASK PINTx INTERRUPT
UNMASK EVT_IVGX
ASSIGN PORT PINS TO
APPROPRIATE PINTx BLOCK
WRITE PINT_EDGE_CLEAR LEVEL
TO SET APPROPRIATE BITS FOR
LEVEL SENSITIVITY
CLEAR PONTENTIAL LATCHES
UNMASK PINTx INTERRUPT
WRITE PORT_INEN TO SET APPROPRIATE
BITS TO ENABLE THE INPUT DRIVERS
Description
Port x GPIO Data Register
Port x GPIO Data Clear Register
Port x GPIO Data Set Register
Port x GPIO Output Toggle Register
Port x GPIO Direction Register
Port x GPIO Direction Clear Register
Port x GPIO Direction Set Register
Port x Function Enable Register
Port x Function Enable Clear Register
Port x Function Enable Set Register
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
B
EDGE OR EDGE WRITE PINT_EDGE_SET
LEVEL SENSITIVE TO SET APPROPRIATE BITS FOR
EDGE SENSITIVITY
DUE TO HISTORY
DONE