Analog Devices ADSP-SC58 Series Hardware Reference Manual page 959

Programming Model for Three-Phase AC Motor Control
• Disable all outputs (PWM_ACTL.DISHI through PWM_CCTL.DISHI =0, PWM_ACTL.DISLO
through PWM_CCTL.DISLO =0)
• Use conventional PWM, disable crossover (PWM_ACTL.XOVR through PWM_CCTL.XOVR =0)
• Use symmetrical pulse position on all outputs (PWM_ACTL.PULSEMODEHI through
PWM_CCTL.PULSEMODEHI =0, PWM_ACTL.PULSEMODELO through
PWM_CCTL.PULSEMODELO =0)
• Set an initial duty-cycle of 50%
PWM Enable for Motor Control
The processor must do the following programming to enable the PWM before starting the motor.
1. Start the PWM timer TMR0 using the
ADDITIONAL INFORMATION: This operation has the same effect as setting the PWM_CTL.GLOBEN bit
=1.
2. Enable six PWM outputs using the following bitwise operations on the
isters.
PWM_ACTL|=0x3
PWM_BCTL|=0x3
PWM_CCTL|=0x3
ADDITIONAL INFORMATION: These operations have the same effect as enabling high and low-side channel
outputs by setting the PWM_ACTL.DISHI through PWM_CCTL.DISHI bits =1 and the
PWM_ACTL.DISLO through PWM_CCTL.DISLO bits =1.
3. Enable the PWM TRIP0 interrupt using the
register.
ADDITIONAL INFORMATION: This operation has the same effect as setting the PWM_ILAT.TRIP0 bit
=1
PWM Response to Sync Interrupt for Motor Control
When the PWM sync interrupt occurs, the processor could need to update to the PWM duty cycle with a value
calculated by the motor control algorithm. This application uses symmetric pulses position and uses dependent high
and low-side output. So, the PWM updates only one register for each phase.
1. Write the new duty cycle value (calculated by motor control algorithm) to the timer when the sync interrupt
occurs.
The following bitwise operations on the
19–38
(PWM_AH0 throughPWM_CH0
PWM_CTL |=0x1 bitwise operation on the
PWM_ILAT |= 0x1 bitwise operation on the
PWM_AH0 through
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
=0x0)
PWM_ACTL
PWM_CH0 registers accomplish this task:
PWM_CTL register.
through PWM_CCTL reg-
PWM_ILAT