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SPI Functional Description
Changing to quad SPI mode must be done when the SPI is in a quiescent state.
While using dual or quad I/O mode for communicating with flash devices, program the SPI_CTL.CPHA and the
SPI_CTL.CPOL bits =1. This programming avoids bus contention during read operations, because the flash de-
vice starts driving out the bits immediately after dummy cycles in read header.
Figure 16-10: Quad Mode Timing for CPHA=0, SOSI=1, 16-Bit Transfer, LSBF=0.
NOTE:
The SPI does support quad SPI 8-bit transfer in slave continuous mode of operation with an
SCLK:SPI_CLK ratio of less than 1:2. A minimum of 2 SCLK cycles is required between transfers in 8-
bit quad SPI slave mode with an SCLK:SPI_CLK ratio of less than 1:2.
Fast Mode
Fast mode is similar to the normal mode of operation when transmitting. When receiving, data is sampled at the
next transmit edge allowing a full cycle of timing in the receive direction. This mode is valid in master mode opera-
tion only. When the SPI operates in fast mode, the slave drives the data for one full cycle.
Figure 16-11: SPI Transfer Protocol in Fast Mode for SPI_CTL.CPHA = 0
16–14
1
Cycle
Number
SPI_CLK
(CPOL=0)
SPI_CLK
(CPOL=1)
SPI_MOSI/
MSB
D0
SPI_MISO/
14
D1
13
D2
12
D3
Slave
Select
Mstr,slave
drive MSB
already
CPOL=0
CPOL=1
MOSI
D7
D5
D6
MISO
D7
D6
D5
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
3
4
2
3
11
7
10
6
2
1
9
5
8
4
LSB
D1
D0
D4
D3
D2
D1
D0
D4
D3
D2
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