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ADSP-SC58x EPPI Register Descriptions
Clock Divide Register
The
register provides the divisor for EPPI internal clock generation. The generated clock frequen-
EPPI_CLKDIV
cy is given by following formula:
EPPI_CLK = (SCLK1_0) /
Note that a value of 0xFFFF is invalid for the
Figure 18-14: EPPI_CLKDIV Register Diagram
Table 18-48: EPPI_CLKDIV Register Fields
Bit No.
(Access)
15:0
VALUE
(R/W)
18–54
(EPPI_CLKDIV
+ 1)
EPPI_CLKDIV
15
14
13
0
0
0
VALUE (R/W)
Internal Clock Divider
31
30
29
0
0
0
Bit Name
Internal Clock Divider.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register.
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
4
3
2
1
0
0
0
0
0
0
20
19
18
17
16
0
0
0
0
0
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