Analog Devices ADSP-SC58 Series Hardware Reference Manual page 57

Sharc+ processor
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Endpoint Base Address Register 1 ........................................................................................................ 29–168
Endpoint Base Address Mask Register 2 .............................................................................................. 29–169
Endpoint Base Address Register 2 ........................................................................................................ 29–170
Endpoint Base Address Mask Register 3 .............................................................................................. 29–171
Endpoint Base Address Register 3 ........................................................................................................ 29–172
Endpoint Base Address Mask Register 4 .............................................................................................. 29–173
Endpoint Base Address Register 4 ........................................................................................................ 29–174
Endpoint Base Address Mask Register 5 .............................................................................................. 29–175
End Point Base Address Register 5 ....................................................................................................... 29–176
Capability Pointer Register .................................................................................................................. 29–177
Class Code and Revision ID Register ................................................................................................... 29–178
End Point Configuration Register ....................................................................................................... 29–179
CardBus CIS Pointer Register .............................................................................................................. 29–180
Device Capabilities Register ................................................................................................................ 29–181
Device ID and Vendor ID Register ...................................................................................................... 29–184
Interrupt Line and Pin Register ........................................................................................................... 29–185
End Point Expansion ROM Base Address Register .............................................................................. 29–186
Subsystem ID and Subsystem Vendor ID Register ............................................................................... 29–187
Command and Status Register ............................................................................................................. 29–188
Error Source Identification Register ..................................................................................................... 29–192
Filter Mask 2 Register .......................................................................................................................... 29–193
Link Width and Speed Change Control Register ................................................................................. 29–194
Header Log Register 0 ......................................................................................................................... 29–197
Header Log Register 1 ......................................................................................................................... 29–198
Header Log Register 2 ......................................................................................................................... 29–199
Header Log Register 3 ......................................................................................................................... 29–200
iATU Region Control 1 Inbound Register ........................................................................................... 29–201
iATU Region Control 1 Outbound Register ........................................................................................ 29–203
iATU Region Control 2 Inbound Register ........................................................................................... 29–205
iATU Region Control 2 Register Outbound ........................................................................................ 29–209
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
lvii

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