Analog Devices ADSP-SC58 Series Hardware Reference Manual page 496

SMC_AOE signal as the address valid signal (SMC_NORDV). The SMC_AOE signal asserts during the setup period,
unlike in asynchronous SRAM writes where the SMC_AOE signal never asserts.
Asynchronous Flash Page Mode Reads
The Asynchronous Page Mode Read Bus Cycle figure shows an asynchronous page mode bus read cycle for a burst of
five reads. The reads are split into four reads followed by a single read.
CLKOUT
NOR_An
NOR_CE
NOR_ADV
NOR_OE
NOR_DQ15-0
Figure 11-10: Asynchronous Page Mode Read Bus Cycle
The programmed bank parameters are:
• Read setup time = 2 cycles
• Read access time = 6 cycles
• Page wait = 2 cycles
• Hold time =2 cycles
The maximum number of read bursts in a total page access depends on the bank SMC_B0CTL.PGSZ bits (00 =4
words, 01 =8 words, 1x =16 words). The first read access is extended for three more page-read cycles whose period is
equal to the page wait states. Besides the start of the setup phase, the read address is incremented at the start of every
page cycle. Read data is latched with the falling edge of CLKOUT the end of the read access period, and also at the
end of the page cycles.
Asynchronous FIFO Reads and Writes
The Asynchronous FIFO Read Bus Cycles figure shows the read bus cycles for an asynchronous FIFO device. The
SMC bank is programmed in asynchronous SRAM mode, with SMC_B0CTL.SELCTRL =01 (SMC_AMS[n] is
OR'ed with SMC_ARE).
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Read
Data
Latched
A0
D0
Read Read
Setup Access
2 Cycles 6 Cycles 2 Cycles
Read Read Read
Data Data Data
Latched Latched Latched
A0+1 A0+2 A0 + 3
D1
D2 D3
Page Page Page Read
Access Access Access Hold
2 Cycles 2 Cycles 2 Cycles 2 Cycles
SMC Programmable Timing Characteristics
Read
Data
Latched
A0 + 4
D4
Read Read Read
Setup Access
6 Cycles 2 Cycles
Hold
11–15