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UART Operating Modes
NOTE:
If the address bit and parity bit are both enabled, the parity check and generation includes the address bit
in its parity calculation.
UART Data Transfer Modes
The UART can transfer data using both the core and DMA. Receive and transmit paths operate independently ex-
cept that the bit rate and the frame format are identical for both transfer directions. Transmit and receive channels
are both buffered. The
UART_THR
register buffers the receive shift register (UART_RSR).
UART Mode Transmit Operation (Core)
In core mode, the processor core moves data to and from the UART. A write to the
transmit operation. If no former operation is pending, the
UART_TSR
register. There, it is shifted out at the bit rate characterized by the
and parity bits appended as defined by the
The
UART_THR
register and the
nificant bit (LSB) always transmits first. This bit is bit 0 of the value written to the
UART Mode LIN Break Command
Some UART-based protocols demand synchronization methods that are not native to standard UART implementa-
tions. For example, the Local Interconnect Network (LIN) protocol requires a low-pulse of well-defined transmit
length as a prologue to every multi-byte message. Its length must be at least 13 bit-times.
With previous UARTs, there were two options to implement this protocol:
• A null byte is transmitted with a temporarily lowered bit rate, or
• A software counter generates the period and the asynchronous set break (SB) mechanisms pull the transmit pin
low
Since both methods have their disadvantages, the newer UART introduces a new inter-frame gap technique.
The feature is not available in MDB or IrDA operating modes. However, in standard UART mode (bits
UART_CTL.MOD [5:4] =00), a write to the
If the transmit buffer is not empty, the UART first transmits all bytes in the queue. It only initiates with pulse gener-
ation after the last stop bit of the last byte has been shifted out.
The value written into the
[6:0] control the duration in bit-times and bit [7] controls the value (duration = UART_TAIP[6:0] /
UART_CLK[15:0]). If UART_TAIP[7] is set, and an active high pulse is issued, the number of stop bits is exten-
ded. If UART_TAIP[7] is cleared, a low pulse is generated. Invert the polarity using the UART_CTL.FCPOL bit.
Writing a value of 13 into the
If the UART_CTL.TPOLC bit is enabled, an inverted most-significant bit can be transmitted.
NOTE:
17–12
register buffers the transmit shift register (UART_TSR) and the
UART_CTL
UART_TSR
register can be modeled as a two-stage transmit buffer. The least sig-
UART_TAIP
UART_TAIP
register defines the nature and the duration of the transmitted pulse. Bits
register generates the break command as required by the LIN protocol.
UART_TAIP
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
UART_THR
register passes the data immediately to the
UART_CTL
register.
register initiates the transmission of an inter-frame pulse.
UART_RBR
register initiates the
UART_THR
register, with start, stop,
UART_THR
register.
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