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Priority ID Register 1
The
register allows transactions from selected masters that generate specific SCB IDs to obtain higher
DMC_PRIO
priority than the transactions proceeding in the usual fashion. The contents of the register are masked with the con-
tents of the
DMC_PRIOMSK
Figure 10-16: DMC_PRIO Register Diagram
Table 10-25: DMC_PRIO Register Fields
Bit No.
(Access)
31:0
ID1
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register to obtain a single SCB ID or a range of IDs that get elevated priority.
15
14
0
0
ID1[15:0] (R/W)
SCB ID1 that Requires Elevated Priority
31
30
0
0
ID1[31:16] (R/W)
SCB ID1 that Requires Elevated Priority
Bit Name
SCB ID1 that Requires Elevated Priority.
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x DMC Register Descriptions
5
4
3
2
1
0
0
0
0
0
0
0
21
20
19
18
17
16
0
0
0
0
0
0
10–53
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