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• UART_STAT.FE bits
• UART_STAT.BI bits
•
register
UART_RBR
The UART_STAT.OE bit is updated as soon as an overflow condition occurs (for example when a stop bit for a
frame is received and the receive FIFO is full). When software does not read the
received data is protected from being overwritten by new data until software clears the UART_STAT.OE bit. Only
the content of the
UART_RSR
The UART module uses the UART_STAT.RFCS bit to monitor the state of the 8-deep receive FIFO. It uses the
UART_CTL.RFIT bit to control the behavior of the buffer. If UART_CTL.RFIT is zero, the
UART_STAT.RFCS bit is set when the receive buffer holds four or more words. If UART_CTL.RFIT is set, the
UART_STAT.RFCS bit is set when the receive buffer holds seven or more words. Hardware clears the
UART_STAT.RFCS bit when a core or DMA reads the
the level of four (UART_CTL.RFIT=0) or seven (UART_CTL.RFIT=1). If the associated interrupt bit
UART_IMSK.ERFCI is enabled, a status interrupt request is reported when the UART_STAT.RFCS bit is set.
If errors are detected during reception, an interrupt can be requested from the status interrupt output. This status
interrupt request goes directly to the SEC. The bit enables status interrupt requests.
The controller detects the following error conditions, shown with their associated bits in the
• Overrun error (UART_STAT.OE bit)
• Parity error (UART_STAT.PE bit)
• Framing error or invalid stop bit (UART_STAT.FE bit)
• Break indicator (UART_STAT.BI bit)
Status Interrupts
The UART module uses status interrupt channels for the following purposes:
• Line status interrupt requests
• Flow control interrupt requests
• Receive FIFO threshold interrupt requests
• Transmission finished interrupt request
The UART module uses the UART_IMSK.ELSI bit to enable the line status interrupts. If set, the status interrupt
request is asserted with one of the UART_STAT.BI, UART_STAT.FE, UART_STAT.PE, or UART_STAT.OE
receive errors bits. A W1C operation to the
cleared, the interrupt request deasserts.
The UART module uses the UART_IMSK_SET.ERFCI bit to enable the receive FIFO count interrupt. If set, a
status interrupt request is generated when the UART_STAT.RFCS is active. The UART_STAT.RFCS bit
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register can be overwritten in the overrun case.
UART_STAT
UART_RBR
register and when the buffer is flushed below
UART_RBR
register clears the error bits. Once all error conditions are
UART Event Control
register in time, the
UART_STAT
register.
17–21
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