Analog Devices ADSP-SC58 Series Hardware Reference Manual page 216

ADSP-SC58x DPM Register Descriptions
Status Register
The register contains bits that report the state of the module and various errors.
DPM_STAT
PRVMODE (R)
Previous Mode
HVBSYERR (R/W1C)
HV Busy Error
LWERR (R/W1C)
Lock Write Error
Figure 5-5: DPM_STAT Register Diagram
Table 5-9: DPM_STAT Register Fields
Bit No.
(Access)
18 HVBSYERR
(R/W1C)
17 LWERR
(R/W1C)
16 ADDRERR
(R/W1C)
7:4 PRVMODE
(R/NW)
5–12
15 14 13 12 11
0 0 0 0 0
31 30 29 28 27
0 0 0 0 0
Bit Name
HV Busy Error.
The DPM_STAT.HVBSYERR bit indicates that a Read access to the Wake Status or
Restoren registers (during engineering transfers only) while the DPMLV is transferring
registers from the DPMHV. Triggers the DPMLV_PSLVERR interrupt.
Lock Write Error.
The DPM_STAT.LWERR bit indicates that a write transaction attempted an access to
a write protected register. Triggers the DPMLV_PSLVERR interrupt.
Address Error.
The DPM_STAT.ADDRERR bit indicates that a read or write transaction attempted
an access to an unimplemented address or a write transaction attempted an access to a
read only register or accesses are non aligned. Triggers the DPMLV_PSLVERR inter-
rupt.
Previous Mode.
The DPM_STAT.PRVMODE bit field indicates the previous mode of the the module.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
10 9 8 7 6 5 4 3
0 0 0 0 0 0 0 0
26 25 24 23 22 21 20 19
0 0 0 0 0 0 0 0
Description/Enumeration
0 Inactive
1 Active
0 Inactive
1 Active
0 Inactive
1 Active
2 1 0
0 0 1
CURMODE (R)
Current Mode
18 17 16
0 0 0
ADDRERR (R/W1C)
Address Error