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Memory-Mapped Mode (SPI2 only)
Table 16-11: SPI Control (SPI_CTL) Register
Bits
SPI_CTL.MSTR
SPI_CTL.PSSE
SPI_CTL.ODM
SPI_CTL.CPHASPI_
CTL.CPOL
SPI_CTL.ASSEL
SPI_CTL.SELST
SPI_CTL.EMISO
SPI_CTL.SIZE
SPI_CTL.LSBF
SPI_CTL.FCEN
SPI_CTL.FCCH
SPI_CTL.FCPL
SPI_CTL.FCWM
SPI_CTL.FMODE
SPI_CTL.SOSI
Table 16-12: SPI Receive Control Register
Bits
SPI_RXCTL.REN
SPI_RXCTL.RTI
SPI_RXCTL.RWCEN
SPI_RXCTL.RDR
SPI_RXCTL.RDO
SPI_RXCTL.RRWM
SPI_RXCTL.RUWM
16–26
Typical values to set
Description
1
Master mode enable
0
Protected slave select ena-
ble
0
Open-drain mode enable
0–0 or 1–1
SPI mode of communica-
tion
1
Hardware slave select pin
control
1
Slave select asserted be-
tween transfers
1
MISO pin enable
2
32-bit transfer size
0
MSB bit first mode
0
Hardware flow control re-
lated bits
1
Fast mode enable
0
Treat SPI_MOSI pin as
IO0 pin.
Typical values to set
Description
1
Receive channel enable
0
Receive transfer initiation disable
0
Receive word counter disable
0
Receive data request disable
0
Discard incoming data if RFIFO is full
0
Receive FIFO regular watermark
0
Receive FIFO urgent watermark disable
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Comments
Flash dependent, usually SPI flash supports
mode-0 (CPHA=CPOL=0) and mode-3
(CPHA=CPOL=1)
Flash dependent, usually SPI flash commu-
nicates in MSB bit first mode
Typically set to 1 for full cycle timing, 0 only
works at low speed
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