Analog Devices ADSP-SC58 Series Hardware Reference Manual page 386

ADSP-SC58x L2CTL Register Descriptions
Table 9-6: L2CTL_CTL Register Fields (Continued)
Bit No.
(Access)
9 ECCMAP1
(R/W)
8 ECCMAP0
(R/W)
7 BK7EDIS
(R/W)
6 BK6EDIS
(R/W)
5 BK5EDIS
(R/W)
4 BK4EDIS
(R/W)
3 BK3EDIS
(R/W)
9–14
Bit Name
ECC Map Bank 1.
The L2CTL_CTL.ECCMAP1 bit selects whether L2 bank 1 addresses ECC RAM or
data RAM.
ECC Map Bank 0.
The L2CTL_CTL.ECCMAP0 bit selects whether L2 bank 0 addresses ECC RAM or
data RAM.
Bank 7 ECC Disable.
The L2CTL_CTL.BK7EDIS bit disables L2 bank 7 ECC operation.
Bank 6 ECC Disable.
The L2CTL_CTL.BK6EDIS bit disables L2 bank 6 ECC operation.
Bank 5 ECC Disable.
The L2CTL_CTL.BK5EDIS bit disables L2 bank 5 ECC operation.
Bank 4 ECC Disable.
The L2CTL_CTL.BK4EDIS bit disables L2 bank 4 ECC operation.
Bank 3 ECC Disable.
The L2CTL_CTL.BK3EDIS bit disables L2 bank 3 ECC operation.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 Data RAM
1 ECC RAM
0 Data RAM
1 ECC RAM
0 Enable ECC
1 Disable ECC
0 Enable ECC
1 Disable ECC
0 Enable ECC
1 Disable ECC
0 Enable ECC
1 Disable ECC
0 Enable ECC
1 Disable ECC