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7 System Event Controller (SEC) and Generic
Interrupt Controller (GIC)
There are two interrupt controllers—a generic interrupt controller (GIC) for the ARM core and the system event
controller (SEC) for the SHARC cores.
System event management is the responsibility of the system event controller (SEC). The SEC manages the configu-
ration of all system event sources. The SEC also manages the propagation of system events to all connected cores
and the system fault interface.
All of the peripheral interrupts are routed using a single SEC interrupt to the desired core. The SEC allows pro-
grammability of the peripheral interrupt's priority, supporting up to 256 priority levels that are arbitrated within the
SEC itself. The SEC also allows these interrupts to be grouped and masked by priority level and provides the flexi-
bility to choose which core(s) the interrupt is routed to.
The SEC also supports self-nesting of interrupts, which is required when sharing a single interrupt request to an
individual core, as this allows for a higher-priority peripheral interrupt to be passed to the core while it is currently
servicing a lower-priority peripheral interrupt. For more details please refer to "Self-Nesting Mode for System Event
Controller Interrupt (SECI)" in the SHARC+ Core Programming Reference.
For more information about the ARM GIC, visit the ARM Information Center.
SEC Features
The following list describes the system event controller features.
• Comprehensive system event source management including interrupt enable, fault enable, priority, core map-
ping, and source grouping.
• Fault management including fault action configuration, timeout, external indication, and system reset.
• Determinism where all system events have the same propagation delay and provide unique identification of a
specific system event source.
• Distributed programming model where each system event source control and all status fields are independent
of all others.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
System Event Controller (SEC) and Generic Interrupt Controller (GIC)
7–1
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