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CGU (DCLK) INITIALIZATION
SELF REFERSH MODE
DMCx_PHY_CTL0.RESETDLL
INITIALIZE CGU TO CHANGE
THE DCLK FREQUENCY
DMCx_PHY_CTL0.RESETDLL
WAIT 9000 DCLK CYCLES
FOR DLL TO LOCK
BRING DMC OUT OF
SELF REFRESH MODE
ENSURE THAT BITS 3-0 OF THE DMCx_PHY_CTL0
REGISTER AND BITS 31-26 OF THE DMCx_PHY_CTL2
ARE SET DMCx_PHY_CTL0 = 0x0000000F,
FOR DDR3 MODE, SET BIT 1 AND CONFIGURE
CONFIGURE ODT AND DRIVE IMPEDANCE VALUES
IN THE DMCx_CAL_PADCTL2 REGISTER. ENSURE THE
RTTCALEN, PDCALEN, PUCALEN BITS IN
DMCx_CAL_PADCTL0 ARE SET (THEY ARE SET AT RESET).
SET DMCx_PHY_CTL1.BYPODTEN BIT IF NO ODT REQUIRED.
SET DMCx_CAL_PADCTL0.CALSTART BIT TO
START THE ODT AND DRIVE IMPEDANCE CALIBRATION
Figure 10-1: DMC Initialization Flow
The DMC accumulates system crossbar transactions that occur during or before initialization and sends them to
SDRAM once the SDRAM initialization or DLL calibration is complete.
NOTE:
During the DMC PHY DLL calibration, a particular set of locations in the DRAM is written followed
immediately by a series of reads. The DMC PHY needs information about the data to be read during the
PHY DLL calibration prior to the operation. The controller performs one burst write operation to the ad-
dress programmed in the
during memory initialization.
If calibration of the PHY is performed when the DRAM contains valid data, ensure that this address
points to an unused address. Otherwise, this operation modifies application data stored at the address se-
lected. The DLL calibration modifies all 16 bytes corresponding to the 16-byte aligned address, even if the
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
PLACE DMC IN
SET
Y
BIT
CLEAR
BIT
Y
DDR CONTENT
NEED TO BE
PRESERVED?
DMC IS IN
N
SELF-REFRESH
MODE?
Y
DMCx_PHY_CTL2 = 0xFC000000
BITS 5-2 OF DMCx_PHY_CTL WITH
WL=CWL + AL IN DCLK CYCLES
WAIT 300 DCLK CYCLES FOR PAD
CALIBRATION TO COMPLETE
DMC PHY INITIALIZATION
DMC_DT_CALIB_ADDR
DMC CONTROLLER INITIALIZATION
START
FIRST TIME
INIT. AFTER
POWER-UP
RESET?
N
Y
DCLK CHANGE
REQUIRED?
N
N
FIRST TIME
N
INIT. AFTER POWER-UP
RESET?
OR PAD RECALIB
REQUIRED?
Y
SET DDR MODE TO
DDR3/2/LPDDR IN
DMCx_PHY_CTL4
REGISTER
ENSURE DMCx_PHY_CTL3
BITS 6, 7, 25, AND 27 ARE SET
N
LPDDR MODE?
Y
SET
DMCx_PHY_CTL1.BYPODTEN
BIT
register. The exact address chosen does not matter
DMC Programming Model
PROGRAM THE DMCx_CFG,
DMCx_TR2-0, DMCx_MR (DDR2/LPDDR),
DMCx_MR0 (DDR3), DMCx_EMR1 (DDR2),
DMCx_MR1 (DDR3), DMCx_EMR2
(DDR2), DMCx_EMR (LPDDR), DMCx_MR2 (DDR3)
ENSURE THE DMC_DT_CALIB_ADDR
REGISTER IS PROGRAMMED TO AN UNUSED
DMC LOCATION (DEFAULT IS THE
START ADDRESS OF THE DMC
ADDRESS RANGE)
PROGRAM THE DMCx_CTL REGISTER WITH
INIT BIT SET TO START THE
DMC INITIALIZATION SEQUENCE
WAIT FOR DMC INITIALIZATION TO
COMPLETE BY POLLING
DMCx_STAT_INITDONE BIT
PROGRAM THE DMCx_CTL.DLLCTL
BIT FIELD = 0x948 (DATACYC=9,
DLLCALRDCNT=72)
N
ANOMALY #0000037
APPLIES?
Y
PERFORM DUMMY READ
TO ANY LOCATION
SET
DMCx_PHY_CTL0.RESETDAT
BIT
CLEAR
DMCx_PHY_CTL0.RESETDAT
BIT
END
10–21
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