PLL Control Register .............................................................................................................................. 3–26

Revision ID Register ................................................................................................................................ 3–28

System Clock Buffer Disable Register ...................................................................................................... 3–29

System Clock Buffer Status Register ........................................................................................................ 3–31

Status Register ......................................................................................................................................... 3–33

Time Stamp Counter 32 LSB Register ..................................................................................................... 3–36

Time Stamp Counter 32 MSB Register ................................................................................................... 3–37

Time Stamp Control Register .................................................................................................................. 3–38

Time Stamp Counter Initial 32 LSB Value Register ................................................................................. 3–39

Time Stamp Counter Initial MSB Value Register .................................................................................... 3–40

Clock Distribution Unit (CDU)

CDU Features................................................................................................................................................ 4–1

CDU Functional Description......................................................................................................................... 4–1

CDU Block Diagram.................................................................................................................................. 4–1

CDU Definitions........................................................................................................................................ 4–2

CDU Clock Configuration Options ........................................................................................................... 4–3

CDU Programming Model ............................................................................................................................ 4–6

Changing the PLL and Clock Frequency .................................................................................................... 4–6

Changing the Clock Frequency................................................................................................................... 4–7

ADSP-SC58x CDU Register Descriptions .................................................................................................... 4–8

CDU Configuration .................................................................................................................................. 4–9

CLKIN Select .......................................................................................................................................... 4–10

CDU Revision ID .................................................................................................................................... 4–11

CDU Status ............................................................................................................................................. 4–12

Dynamic Power Management (DPM)

DPM Features................................................................................................................................................ 5–1

DPM Functional Description ........................................................................................................................ 5–1

ADSP-SC58x DPM Register List ............................................................................................................... 5–1

ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference

Table of Contents