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Shared Peripheral Interrupt Pending Set Register
The
GICDST_SPI_PND_SET[n]
VALUE[31:16] (R/W)
Set Pending Interrupt
Figure 7-45: GICDST_SPI_PND_SET[n] Register Diagram
Table 7-46: GICDST_SPI_PND_SET[n] Register Fields
Bit No.
(Access)
31:0
VALUE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register provides a set-pending bit for each interrupt supported by the GIC.
15
0
VALUE[15:0] (R/W)
Set Pending Interrupt
31
0
Bit Name
Set Pending Interrupt.
Writing 1 to a GICDST_SPI_PND_SET[n].VALUE bit sets the status of the cor-
responding peripheral interrupt to pending. Reading a bit identifies whether the inter-
rupt is pending.
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
30
29
28
27
26
25
24
23
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x GICDST Register Descriptions
6
5
4
3
2
1
0
0
0
0
0
0
0
0
22
21
20
19
18
17
16
0
0
0
0
0
0
0
7–77
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