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Timer Units
NOTE:
In the operation discussed in this section, double-buffering of all channel registers and the timer registers
takes place at the period boundary of the respective timers.
Phase Offset Control
The PWM timers (PWMTMR1 through PWMTMR4) can operate with a programmable phase lag relative to the
main timer, PWMTMR0. To implement phase offset for a channel, use the counter-registers for channel delay
(PWM_DLYA
- PWM_DLYD) with the PWMTMR0 and set the PWM_CTL.DLYAEN bit to l.
Phase offset works as follows.
1. If phase lag is used for channel A (and channel A uses PWMTMR1 to generate a duty cycle), when
PWMTMR0 reaches its period boundary, it triggers the
ber SCLK0_0 cycles that are equal to the value programmed in the
2. At the end of this count, the
tion pulse in every period of PWMTMR0 at a point delayed from its period boundary by the value in the
PWM_DLYA
register.
For more information on how channels can reference different timers for their outputs, see
Unit.
NOTE:
Satisfy the following conditions when using this feature on timer y for channel Y relative to PWMTMRx.
• Program the PWM_DLY[n] register to a value less than 2 × PWM_TM[n].
•
PWM_TM0
The function of PWM_TM[n] (PWMTMR1 in the example) differs in cases where
1) to cases where
PWM_TM0
Case 1: PWM_TM0 = PWM_TMy
When
PWM_TM0
= PWM_TMy, PWMTMRy restarts its period after receiving the synchronization pulse from the
channel delay register (PWM_DLY[n]). If the trigger from the PWM_DLY[n] register is late, PWMTMRy holds its
count until the trigger occurs. If the trigger is a bit early, PWMTMRy reloads without regard to whether it has com-
pleted its current period. As a result, PWMTMRy resyncs with PWMTMR0 with the phase lag programmed in the
PWM_DLYA
register in every one of its periods.
In this case, the expiration of the delay registers (PWM_DLY[n]) is the period boundary of PWMTMRy. Now, all
the double buffered registers related to the given channel update (except the delay registers which are double buf-
fered at the period boundary of PWMTMR0).
The Phase Offset Control Using DELAY figure shows an example where:
• PWM_TM0, PWM_TM1, and
•
and
PWM_DLYA
PWM_DLYB
LAY2 > DELAY1.
19–10
register sends out a trigger to PWMTMR1. It receives a synchroniza-
PWM_DLYA
= N × PWM_TM[n], where N is an integer.
= N ×
(Case 2). The following examples describe both cases.
PWM_TM1
are programmed with the same value.
PWM_TM2
are programmed with values DELAY1 and DELAY2 respectively, such that DE-
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
PWM_DLYA
register. The register counts out the num-
PWM_DLYA
PWM_TM0
register.
Channel Timing Control
=
PWM_TM1
(Case
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