Analog Devices ADSP-SC58 Series Hardware Reference Manual page 684

Block Diagram
Figure 15-2: Link Port Pin Connections
Use external pull-downs for the LP_CLK and LP_ACK pins so that the link port can enable the transmitter and
receiver, irrespective of the state of the other.
Internal Blocks
As shown in the block diagram, the link ports have independent modules for transmit and receive. If enabled as
transmitter, the link port uses a 2 deep 32-bit FIFO. If enabled as a receiver, the port uses a 4 deep 32-bit FIFO.
The core MMR access bus interfaces with these FIFOs. The distributed DMA engines (DDE) use the system cross
bar (SCB) interface to access the FIFO. The link port uses the LP_CTL.TRAN bit to determine whether the mod-
ule is enabled for transmit or receive operation.
Architectural Concepts
The following sections describe the architectural concepts of the link port.
•
Link Port Protocol
•
FIFO Buffers
•
Handshake for Link Port Enable Process
•
Clocking
•
Multi-Processor Connectivity
Link Port Protocol
A link port transmitted word consists of 4 bytes and the communication proceeds as follows.
1. The transmitter asserts the link port clock (LP_CLK) with each byte of data. The receiver uses the falling edge
of LP_CLK driven by the transmitter to latch the byte.
2. When the receiver is ready to accept another word in the receive buffer it asserts the acknowledge signal,
LP_ACK.
3. The transmitter samples LP_ACK driven by the receiver at the beginning of each word transmission. If
LP_ACK is deasserted, then the transmitter does not transmit the next word.
4. The transmitter leaves LP_CLK high and continues to drive the first byte of the next word until LP_ACK is
asserted.
15–4
TRANSMITTER RECEIVER
8
LPx_D7:0
LPx_D7:0
LPx_CLK
LPx_CLK
LPx_ACK
LPx_ACK
X DENOTES THE LINK PORT NUMBER, 0-1
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference